U.S.H.BM EXPERT: A.A. CALCULATES FASTER THAN HBM MEMORY WALL PROBLEMS CONTINUE TO INCREASE

“The memory wall still exists and may even deteriorate further.” Ragu Sriramaneni, an expert in the design of HBM, presented this point at the semiconductor academic conference organized at Stanford University, United States of America, on 23 local time, at Hot Chips 2026. The memory wall refers to the rapid increase in the capacity of the chip responsible for the operation, but the memory responsible for the transmission of data does not keep up with the rate of operation, resulting in performance bottlenecks. This bottleneck, rather than abating it, has grown even more acute after the age of artificial intelligence. Srilamaneni states that the performance of the AI accelerator has increased approximately three times every two years, but that the HBM (high bandwidth memory) that is responsible for the data supply has increased less than two times over the same period. Even if a chip with greater capacity of operation is carried, if the data transmission channel is narrow, the final performance is bound by the speed of the route. He predicted that: “Breaking the boundary between the computing unit and the memory, the new architecture design would be a path to overturning the memory wall.”